CTL for Test Information of Digital ICsSpringer Science & Business Media, 8 Mei 2007 - 173 halaman CTL is a language that is used to represent test information. It is being developed as a standard within the IEEE framework. The proposed standard IEEE 1450.6 namely the Core Test Language (CTL) has its beginnings in the IEEE 1500 standardization activity as the language to represent test information about a core. The language has been designed to be generally applicable for a number of activities in digital IC testing. This book is focused on describing CTL. CTL for Test Information of Digital ICS is an example-oriented book on CTL that is written with the goal of getting the reader to think like the creators of CTL. Most of the explanations are limited to very simple examples so that the netlist (design) can be drawn out for better visualization of the concepts. There are two types of example CTL syntax in this book. Examples that explain the use of CTL and examples that describe syntax and semantics of the language as it is being introduced. This book should be read by anyone who is interested in testing integrated circuits. The contents of this book are especially relevant to the segment of the industry that is developing cores and/or using cores in system-on-chip methodologies. |
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ActiveState associated AssumedInitialState ATPG ATPG-FS tools block of statements boundary CaptureClock clock clock signal configuration connection constructs core instance CORE_INST_NAME CoreInstance CoreType CTL block CTL CTL_NAME CTL information CTL syntax data types data_type_enum DataRateForProtocol DataType TestData default defined described in CTL design entities domain DOMAIN_NAME DomainReferences enable signal enabling condition Environment block Environment ENV_NAME EstablishMode example ExpectHigh Figure flip-flop ForceDown ForceUp hierarchical identified IEEE incomplete syntax shown initProtocol inputs integrated Internal block IsConnected keywords language LaunchClock logic logic value logic-1 Macro protocol Macro test_sequence MacroDefs MasterClock memory elements multiple netlist outputs parameters PatternBurst PatternExec PatternInformation block represent reuse scan cells scan chain scan-in ScanCells ScanDataType ScanLength ScanMasterClock ScanOut ScanStructures sequence Shift signal names SignalGroups SIGNALNAME Signals block SignalVariable sigref_expr soc_in specified statement allows STIL test automation test information test mode test patterns TestControl top level User USER_DEFINED values Verilog waveform characters wrapper cell